This disclosure generally relates to phase lock loop circuits.
A phase lock loop (PLL) circuit is an electronic control circuit that generates an output clock signal having a phase that is locked to the phase of an input reference signal. For example, a PLL can be used to adjust an oscillator so that a frequency and phase of a signal generated by the oscillator matches the frequency and phase of a reference input signal. A PLL circuit is commonly used in communication devices, computers, and other electronic devices. An analog PLL circuit uses analog components to provide the phase lock architecture. These analog components include a phase detector, a voltage-controlled oscillator (VCO), and a feedback path between the VCO output signal and an input port of the phase detector. By connecting the input reference signal to another input port of the phase detector, the output of the phase detector may be used to adjust the phase and/or the frequency of the VCO output signal until that phase and/or frequency is locked to the input reference signal.
A PLL circuit may also be implemented using all digital components. Such a PLL circuit is known as an all-digital PLL (ADPLL) circuit. Like its analog counterpart, an ADPLL circuit uses a feedback path to return a digitally-controlled oscillator (DCO) clock signal to generate a digital phase error signal based on the output from a time-to-digital converter (TDC) and a reference phase signal. In response to the digital phase error signal, the phase of the DCO clock signal is adjusted.
Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally indicate identical, functionally similar, and/or structurally similar elements.